ht27c512 otp cmos 64k 8-bit eprom block diagram features operating voltage: +5.0v programming voltage C v pp =12.2v 0.2v C v cc =5.8v 0.2v high-reliability cmos technology latch-up immunity to 100ma from -1.0v to v cc +1.0v cmos and ttl compatible i/o low power consumption C active: 30ma max. C standby: 1 m a typ. 64k 8-bit organization fast read access time: 70ns, 90ns and 120ns fast programming algorithm programming time 75 m s typ. two line control ( oe & ce) standard product identification code package type C 28-pin dip/sop C 32-pin plcc commercial temperature range (0 c to +70 c) general description the ht27c512 chip family is a low-power, 512k bit, +5v electrically one-time programma- ble (otp) read-only memories (eprom). or- ganized into 64k words with 8 bits per word, it features a fast single address location program- ming, typically at 75 m s per byte. any byte can be accessed in less than 70ns/90ns with respect to spec. this eliminates the need for wait states in high-performance microprocessor sys- tems. the ht27c512 has separate output en- able ( oe) and chip enable ( ce) controls which eliminate bus contention issues. 1 6th may 99
pin assignment pin description pin name i/o/c/p description a0~a15 i address inputs dq0~dq7 i/o data inputs/outputs ce c chip enable oe/vpp c/p output enable/program voltage supply nc no connection vcc i positve power supply vss i negative power supply ht27c512 2 6th may 99
absolute maximum ratings operation temperature commercial ...................................................................................0 c to +70 c storage temperature......................................................................................................... C65 c to 125 c applied vcc voltage with respect to vss ........................................................................ C0.6v to 7.0v applied voltage on input pin with respect to vss........................................................... C0.6v to 7.0v applied voltage on output pin with respect to vss............................................... C0.6v to v cc +0.5v applied voltage on a9 pin with respect to vss.............................................................. C0.6v to 13.5v applied vpp voltage with respect to vss .......................................................................C0.6v to 13.5v applied read voltage (functionality is guaranteed between these limits) ................ +4.5v to +5.5v note: these are stress ratings only. stresses exceeding the range specified under absolute maxi- mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics read operation symbol parameter test conditions min. typ. max. unit v cc conditions v oh output high level 5v i oh =C0.4ma 2.4 v v ol output low level 5v i ol =2.1ma 0.45 v v ih input high level 5v 2.0 v cc +0.5 v v il input low level 5v C0.3 0.8 v i li input leakage current 5v v in =0 to 5.5v C5 5 m a i lo output leakage current 5v v out =0 to 5.5v C10 10 m a i cc vcc active current 5v ce=v il , f=5mhz, i out =0ma 30 ma i sb1 standby current (cmos) 5v ce=v cc 0.3v 1.0 10 m a i sb2 standby current (ttl) 5v ce=v ih 1.0 ma i pp vpp read/standby current 5v ce= oe=v il , v pp =v cc 100 m a ht27c512 3 6th may 99
programming operation symbol parameter test conditions min. typ. max. unit v cc conditions v oh output high level 5.8v i oh =C0.4ma 2.4 v v ol output low level 5.8v i ol =2.1ma 0.45 v v ih input high level 5.8v 0.7v cc v cc +0.5 v v il input low level 5.8v C0.5 0.8 v i li input load current 5.8v v in =v il , v ih 5.0 m a v h a9 product id voltage 5.8v 11.5 12.5 v i cc vcc supply current 5.8v 40 ma i pp vpp supply current 5.8v ce=v il 10ma capacitance symbol parameter test conditions min. typ. max. unit v cc conditions c in input capacitance 5v v in =0v 8 12 pf c out output capacitance 5v v out =0v 8 12 pf c vpp vpp capacitance 5v v pp =0v 18 25 pf a.c. characteristics read operation symbol parameter test conditions C70 C90 unit v cc conditions min. max. min. max. t acc address to output delay 5v ce= oe=v il 7090ns t ce chip enable to output delay 5v oe=v il 7090ns t oe output enable to output delay 5v ce=v il 3035ns t df ce or oe high to output float, whichever occurred first 5v 25 25 ns t oh output hold from address, ce or oe, whichever occurred first 5v 0 0 ns ht27c512 4 6th may 99
programming operation ta=+25 c 5 c symbol parameter test conditions min. typ. max. unit v cc conditions t as address setup time 5.8v 2 m s t oes ce/vpp setup time 5.8v 2 m s t oeh oe/vpp hold time 5.8v 2 m s t ds data setup time 5.8v 2 m s t ah address hold time 5.8v 0 m s t dh data hold time 5.8v 2 m s t dfp output enable to output float delay 5.8v 0 130 ns t pw pgm program pulse width 5.8v 30 75 105 m s t vcs vcc setup time 5.8v 2 m s t dv data valid from ce 5.8v 150 ns t vr oe/vpp recovery time 5.8v 2 m s test waveforms and measurements for -70, -90 devices: output test load note: c l =100pf including jig capacitance, except for the -45 devices, where c l =30pf. t r , t f < 20ns (10% to 90%) 1.3v (1n914) 3.3k w output pin c l ht27c512 5 6th may 99
functional description programming of the ht27c512 when the ht27c512 is delivered, the chip has all 512k bits in the one, or high state. zeros are loaded into the ht27c512 through the procedure of programming. the programming mode is entered when 12.2 0.2v is applied to the oe/vpp pin and ce is at v il . for programming, the data to be programmed is applied with 8 bits in parallel to the data pins. the programming flowchart in figure 3. shows the fast interactive programming algorithm. the interactive algorithm reduces program- ming time by using 30 m s to 105 m s programming pulses and giving each address only as many pulses as is necessary in order to reliably pro- gram the data. after each pulse is applied to a given address, the data in that address is veri- fied. if the data is not verified, additional pulses are given until it is verified or until the maxi- mum number of pulses is reached. this process is repeated while sequencing through each ad- dress of the ht27c512. this part of the pro- gramming algorithm is carried at v cc =5.8v to assure that each eprom bit is programmed to a sufficiently high threshold voltage. this en- sures that all bits have sufficient margin. after the final address is completed, the entire eprom memory is read at v cc =v pp =5.25 0.25v to verify the entire memory. program inhibit mode programming of multiple ht27c512 in parallel with different data is also easily accomplished by using the program inhibit mode. except for ce, all like inputs of the parallel ht27c512 may be common. a ttl low-level program pulse applied to an ht27c512 ce input with oe/vpp=12.2 0.2v will program that ht27c512. a high-level ce input inhibits the other ht27c512 from being programmed. program verify mode verification should be performed on the pro- grammed bits to determine whether they were correctly programmed. the verification should be performed with oe/vpp and ce at v il . data should be verified at t dv after the falling edge of ce. auto product identification the auto product identification mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by the pro- gramming equipment for the purpose of auto- matically matching the device to be programmed with its corresponding program- ming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the ht27c512. to activate this mode, the programming equip- ment must force 12.0 0.5v on the address line a9 of the ht27c512. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih , when a1=v ih . all other address lines must be held at v ih during auto product identification mode. byte 0 (a0=v il ) represents the manufacturer code, and byte 1 (a0=v ih ), the device code. for ht27c512, these two identifier bytes are shown in the operation mode truth table. all identifiers for the manufacturer and device codes will pos- sess odd parity, with the msb (dq7) defined as the parity bit. when a1=v il , the ht27c512 will read out the binary code of 7f, continuation code, to signify the unavailability of manufacturer id codes. read mode the ht27c512 has two control functions, both of which must be logically satisfied in order to obtain data at outputs. chip enable ( ce) is the power control and should be used for device selection. output enable ( oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs (t oe ) after the falling edge of oe, assuming the ce has been low and addresses have been ht27c512 6 6th may 99
stable for at least t acc -t oe . standby mode the ht27c512 has cmos standby mode which reduces the maximum vcc current to 10 m a. it is placed in cmos standby when ce is at v cc 0.3v. the ht27c512 also has a ttl- standby mode which reduces the maximum vcc current to 1.0ma. it is placed in ttl- standby when ce is at v ih . when in standby mode, the outputs are in a high-impedance state, independent of the oe input. two-line output control function to accommodate multiple memory connections, a two-line control function is provided to allow for: low memory power consumption assurance that output bus contention will not occur. it is recommended that ce be decoded and used as the primary device-selection function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low- power standby mode and that the output pins are only active when data is desired from a particular memory device. system considerations during the switch between active and standby conditions, transient current peaks are pro- duced on the rising and falling edges of chip enable. the magnitude of these transient cur- rent peaks is dependent on the output capaci- tance loading of the device. at a minimum, a 0.1 m f ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and vpp to minimize tran- sient effects. in addition, to overcome the volt- age drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7 m f bulk electrolytic capacitor should be used between vcc and vpp for each eight de- vices. the location of the capacitor should be close to where the power supply is connected to the array. operation mode truth table all the operation modes are shown in the table following. mode ce oe/vpp a0 a9 output read v il v il x (2) x dout output disable v il v ih x x high z standby (ttl) v ih x x x high z standby (cmos) v cc 0.3v x x x high z program v il v pp xx d in program verify v il v il xx d out product inhibit v ih v pp x x high z manufacturer code (3) v il v il v il v h (1) 1c device type code (3) v il v il v ih v h (1) 83 notes: (1) v h = 12.0v 0.5v (2) x=either v ih or v il (3) for manufacturer code and device code, a1=v ih , when a1=v il , both codes will read 7f ht27c512 7 6th may 99
product identification code code pins hex data a0 a1 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer 0 1 000111001c device type 1 1 1000001183 continuation 00011111117f 10011111117f figure 1. a.c. waveforms for read operation figure 2. programming waveforms ht27c512 8 6th may 99
figure 3. fast programming flowchart ht27c512 9 6th may 99
ht27c512 10 may 6, 1999 copyright 1999 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holtek semiconductor (shanghai) ltd. 7th floor, building 2, no.889, yi shan road, shanghai, china tel:021-6485-5560 fax:021-6485-0313 holmate technology corp. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885
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